Traditionally, design space exploration for Systems-on-Chip (SoCs) has focused on the computational aspects of the problem at hand. However, as the number of processing elements on a single chip and their performance continue to increase, the design of the communication architecture plays a central role in defining the area, performance and energy consumption of the overall system. Furthermore, the global interconnects cause unpredictable delays and high power consumption. To mitigate these kinds of effects, the network-on-chip (NoC) communication architectures have emerged recently as a promising alternative to the classical bus-based and point-to-point communication architectures. (Series: CSE Colloquia - 2008)